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CAT28LV65
V CC ? 0.3 V
0.0 V
INPUT PULSE LEVELS
2.0 V
0.6 V
REFERENCE POINTS
Figure 2. A.C. Testing Input/Output Waveform (Note 9)
9. Input rise and fall times (10% and 90%) < 10 ns.
V CC
1.8 K
DEVICE
UNDER
TEST
1. 3 K
OUTPUT
C L = 100 pF
C L INCLUDES JIG CAPACITANCE
Figure 3. A.C. Testing Load Circuit (example)
Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (V CC = 3.0 V to 3.6 V, unles s otherwise specified.)
28LV65 ? 15
28LV65 ? 20
28LV65 ? 25
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
t WC
t AS
t AH
t CS
t CH
t CW (Note 10)
t OES
t OEH
t WP (Note 10)
t DS
t DH
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
Data Setup Time
Data Hold Time
0
100
0
0
110
0
0
110
60
0
5
0
100
0
0
150
10
10
150
100
0
5
0
100
0
0
150
10
10
150
100
0
5
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t INIT (Note 11)
t BLC (Notes 11, 12)
Write Inhibit Period After Power ? up
Byte Load Cycle Time
5
0.05
10
100
5
0.1
10
100
5
0.1
10
100
ms
m s
t RB
WE Low to RDY/BUSY Low
220
220
220
ns
10. A write pulse of less than 20 ns duration will not initiate a write cycle.
11. This parameter is tested initially and after a design or process change that affects the parameter.
12. A timer of duration t BLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however
a transition from HIGH to LOW within t BLC max. stops the timer.
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